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Conference Papers Year : 2020

Binary linear ECCs optimized for bit inversion in memories with asymmetric error probabilities

Abstract

Many memory types are asymmetric with respect to the error vulnerability of stored 0's and 1's. For instance, DRAM, STT-MRAM and NAND flash memories may suffer from asymmetric error rates. A recently proposed errorprotection scheme consists in the inversion of the memory words with too many vulnerable values before they are stored in an asymmetric memory. In this paper, a method is proposed for the optimization of systematic binary linear block error-correcting codes in order to maximize their impact when combined with memory word inversion.
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Dates and versions

cea-03469725 , version 1 (07-12-2021)

Identifiers

Cite

Valentin Gherman, Samuel Evain, Bastien Giraud. Binary linear ECCs optimized for bit inversion in memories with asymmetric error probabilities. DATE 2020 - 2020 Design, Automation & Test in Europe Conference & Exhibition, IEEE, Mar 2020, Grenoble, France. pp.298-301, ⟨10.23919/DATE48585.2020.9116531⟩. ⟨cea-03469725⟩
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