This paper presents a new compressive sensing acquisition scheme well adapted for highly constrained hardware implementations. The proposed sensing model being basically designed to meet both theoretical (i.e., Restricted Isometry Property) and hardware requirements (i.e., power consumption, silicon footprint), is highly suitable for image sensors applications addressing both image rendering and embedded decision making tasks. In fact, for a pixels array, the proposed framework consists in applying for each row a random modulation ±1 and a random permutation of the pixels, and then averaging the outputs by column to extract a compressed vector. This model is shown to be relevant as it has the same theoretical performance as a randomly generated sensing scheme as well as a low silicon footprint for physical implementation. Various numerical results and a discussion on possible implementations will be presented to show the robustness and the efficiency of the proposed model.