Nowadays, High-Performance Computing systems (HPC) need to deliver computational intensity as well as processing complex workloads and applications at high speeds in parallel. It requires computing power and performance, leading to complex architectures, heterogeneity and advanced technology nodes. Therefore, MPSoC design has become increasingly difficult. Chip engineers are facing unprecedented challenges to find the best-case scenario for Power, Performance, and Area (PPA) among billions of possibilities, leading to a Design Space Exploration (DSE) problem. This work proposes a complete framework to ease the next generation of HPC processor designs. By combining competitive simulators VPSim and McPAT for a realistic estimation of Key Performance Indicators with an exploration algorithm such as Bayesian Optimization, we leveraged an Automated Design Space Exploration fully adapted for efficient HPC processor designs based on ARM-v8 architectures. We also demonstrated the potential of Bayesian Optimization to reach Pareto-optimal solutions with only a hundred simulations by being around 5x sample efficient than Genetic Algorithms. Furthermore, the diversity of the obtained Pareto-front enables deep analysis of relevant architectural parameters that significantly impact design performances, thus empowering architects' knowledge for further targeted design exploration and design choices.