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Communication Dans Un Congrès Année : 2022

WIP: A Memory Interference Analysis using a Formal Timing Analyzer

Résumé

Safety-critical applications require well-defined and documented timing behavior. These requirements shape the design and implementation of a timing analyzer based on a formal Instruction-Set Architecture (ISA) semantics and formal micro-architecture models. In this paper we present the key elements of such a timing analyzer and how to systematically combine the formal components to address timing properties such as evaluating memory interferences. We also report preliminary experiments of memory interference analysis of multi-threaded applications in the context of multicore architectures.
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Dates et versions

cea-04487796 , version 1 (04-03-2024)

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Mihail Asavoae, Oumaima Matoussi, Bouachtala Asmae, Hai-Dang Vu, Mathieu Jan. WIP: A Memory Interference Analysis using a Formal Timing Analyzer. LCTES 2022: Proceedings of the 23rd ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems, Jun 2022, San Diego, United States. ⟨10.1145/3519941.3535077⟩. ⟨cea-04487796⟩
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