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Communication Dans Un Congrès Année : 2022

Formal Processor Modeling for Analyzing Safety and Security Properties

Résumé

Thanks to the emergence of open hardware initiatives, the exact behavior of the hardware design can be analyzed and combined with program representations to verify system-level safety and security properties. However, such formal verifications require the design of appropriate abstract models to scale with the complexity of the analyzed computational systems. In this paper, we compare the different needs when designing abstract processor models for the evaluation of timing predictability, a safety property, and for security assessments when considering fault injections. We also report how the process of building these abstract processor models could be automated.
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Dates et versions

cea-04487792 , version 1 (04-03-2024)

Identifiants

  • HAL Id : cea-04487792 , version 1

Citer

Benjamin Binder, Samira Ait Bensaid, Simon Tollec, Farhat Thabet, Mihail Asavoae, et al.. Formal Processor Modeling for Analyzing Safety and Security Properties. Embedded Real Time Systems (ERTS), Mar 2022, Toulouse, France. pp.1-10. ⟨cea-04487792⟩
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