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Communication Dans Un Congrès Année : 2023

Compute-In-Place Serial FeRAM: enhancing performance, efficiency and adaptability in critical embedded systems

Résumé

In an era where embedded systems play an increasingly vital role in critical domains like electric mobility, healthcare, industry, or infrastructure monitoring, the demand for real-time data processing is paramount. This paper addresses the challenges posed by high sensor data rates and limited processing power of microcontrollers (MCUs) in these applications. It introduces a novel computational method leveraging the Serial Ferroelectric RAM (FeRAM) architecture, along with the Computational SRAM concept, and will be called Compute-In-Place (CIP). This exploration of CIP Serial FeRAM reveals its potential for improving predictability, energy efficiency and security in high-throughput processing of large volumes of sensor data. Unlike conventional computing architectures, CIP Serial FeRAM lightens the MCU's computational load, reduces latency and improves energy efficiency by enabling computational tasks within memory. This paper emphasizes the flexibility of CIP Serial FeRAM for diverse real-time tasks, paving the way for more performance, efficient and adaptable critical embedded systems.
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Dates et versions

cea-04463300 , version 1 (16-02-2024)

Identifiants

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Jean-Philippe Noel, Emanuele Valea, Laurent Grenouillet, Bastien Chapuis, Clément Fisher, et al.. Compute-In-Place Serial FeRAM: enhancing performance, efficiency and adaptability in critical embedded systems. VLSI SoC - 2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration, Oct 2023, Dubai, United Arab Emirates. ⟨10.1109/VLSI-SoC57769.2023.10321864⟩. ⟨cea-04463300⟩
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