Communication Dans Un Congrès Année : 2024

A 772μJ/frame imageNet feature extractor accelerator on HD images at 30FPS

Résumé

Many applications benefit from AI inference at the edge, in industry, agriculture and transportation domains. The observed trend in image/video analysis is to increase the resolution of sensors, thus increasing the need for powerful, yet ultra-low power and low-latency hardware solutions. In this paper, we explore a novel approach to meet these conflicting requirements and we propose a whole new class of accelerator: the Feature Extractor Accelerator (FEA). This solution enables processing of HD images (1280x720) at 30 frames per second (FPS), using a fraction of the energy of the actual image sensor: it consumes at most 23.2mW, with a 6.9ms latency, while reaching 70.42% accuracy on ImageNet. This approach combines two key principles: a feature extraction backbone and transfer learning technique.
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Dates et versions

cea-04799430 , version 1 (22-11-2024)

Identifiants

  • HAL Id : cea-04799430 , version 1

Citer

Ivan Miro-Panades, Vincent Lorrain, Lilian Billod, Inna Kucher, Vincent Templier, et al.. A 772μJ/frame imageNet feature extractor accelerator on HD images at 30FPS. APCCAS - Asia Pacific Conference on Circuits and Systems, Nov 2024, Taipei, Taiwan. ⟨cea-04799430⟩
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