Two-level stacked nanowire MOSFETs: A low temperature analysis of the low-field mobility degradation factors - CEA - Commissariat à l’énergie atomique et aux énergies alternatives
Article Dans Une Revue Journal of Integrated Circuits and Systems Année : 2024

Two-level stacked nanowire MOSFETs: A low temperature analysis of the low-field mobility degradation factors

Résumé

This study explores the carrier mobility and its degradation factors in relation to temperature for 2-level stacked nanowire MOSFETs within the temperature range of 100 K to 400 K. The low-field carrier mobility and its degradation factors were extracted using the Y-function. Additionally, it was observed that the peak transconductance is achieved at a higher overdrive voltage (VG-VTH), particularly as the temperature decreases. Notably, the low-field mobility is more sensitive in wider devices. Compared to other technologies such as omega-gate nanowires and planar fully depleted SOI transistors, this technology exhibits less sensitivity of low-field mobility to temperature variations. The first-order degradation factor was observed to decrease with rising temperature, while the second-order factor exhibited an increase within the same temperature range. The variation in the first and second order degradation factors with temperature is more pronounced in wider devices.
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cea-04767402 , version 1 (05-11-2024)

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Jaime Calçade Rodrigues, Mikael Cassé, Sylvain Barraud, Maud Vinet, Olivier Faynot, et al.. Two-level stacked nanowire MOSFETs: A low temperature analysis of the low-field mobility degradation factors. Journal of Integrated Circuits and Systems, 2024, 19 (2), pp.1 - 5. ⟨10.29292/jics.v19i2.816⟩. ⟨cea-04767402⟩
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