New insights using avalanche mode for pn-wafer evaluation of SiC diodes technology and design ruggedness - CEA - Commissariat à l’énergie atomique et aux énergies alternatives
Communication Dans Un Congrès Année : 2024

New insights using avalanche mode for pn-wafer evaluation of SiC diodes technology and design ruggedness

Résumé

We propose a method to test the devices on-wafer using a wafer prober and a HVSMU. In this first study, SiC 1200V-rated 4H-SiC power diodes were considered. Avalanche behavior is observed through a static I(V) reverse bias measurement. Afterwards, the current level at avalanche is recorded and then a new measurement is set to stress this current level for a designated interval of time. We can bias either in voltage or in current, above the avalanche point. High temperature can also be applied to accelerate the relaxation. The main interest of this method is the activation of both electrons and holes currents under high electric field bias. This evidences possible instabilities/drifts which depend on the avalanche breakdown location (active area, and periphery). In summary, the proposed stress in low current avalanche mode performed on-wafer brings new insight into the device characteristics. The possibility to perform the test on-wafer shortens the development phase. This non-destructive test is potentially useful to control the stability of a fabrication process in a production line and the long-term reliability of the device.
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Dates et versions

cea-04754535 , version 1 (25-10-2024)

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Ahmad Abbas, Cyrille Le Royer, Romain Lavieville, Saliou Gningue, Rihab Chouk, et al.. New insights using avalanche mode for pn-wafer evaluation of SiC diodes technology and design ruggedness. ISPSD 2024 - 36th International Symposium on Power Semiconductor Devices and ICs, Jun 2024, Brême, Germany. pp.176-179, ⟨10.1109/ISPSD59661.2024.10579466⟩. ⟨cea-04754535⟩
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