This paper provides a comprehensive study of the impact of the gate recess depth (RD) on the GaN-on-Si MOS-HEMTs DC performances. ID(VG) and ID(VD) measurements, respectively in forward and blocking modes, are carried out at 25° and 150°C. The gate recessed depth (50nm, 150nm, and 350nm) is modulated by adjusting the plasma etching time, which is a critical step for improving the dielectric/GaN interface quality and the gate channel electron mobility. Three distinct regions can be defined separately: the bottom, the sidewall, and the corner region being the junction between the two previous regions. To assess the impact of gate recessed depth (RD) on the several mobilities around the gate cavity first, we applied our previous methodology allowing us to extract the bottom (µbot) and the entire sidewall region mobility (µT), without distinction from the corner (what we called the transverse region). The mobility of the transverse region was found surprisingly to increase with deeper RD. To gain insight into the impact of the RD on this transverse section, a new extraction methodology is proposed to extract separately the gate corner (µcorner) and sidewall (µSW) mobility. These extractions show that the corner mobility is found to be reduced compared to the sidewall one (µcorner<µSW) evidencing the different weighting contributions over the transverse mobility. Moreover, these mobilities are found to be more degraded compared to the bottom one, highlighting the different contributions on the on-state resistance (RON). Indeed, the on-state resistance is lowered with the shallower RD due to the reduced sidewall resistance contribution (lower sidewall length) and despite the incremental contribution of the bottom resistance (larger effective gate length). However, the shallower RD shows an increase in the drain–source leakage current in reason of a lower gate electrostatic control. TCAD simulations of the three RD morphologies are carried out to validate the experimental trends and the proposed methodology.