Experimental Analysis and Modeling of Self-Heating and Thermal Coupling in 28 nm FD-SOI CMOS Transistors Down to Cryogenic Temperatures - CEA - Commissariat à l’énergie atomique et aux énergies alternatives Accéder directement au contenu
Article Dans Une Revue IEEE Transactions on Electron Devices Année : 2024

Experimental Analysis and Modeling of Self-Heating and Thermal Coupling in 28 nm FD-SOI CMOS Transistors Down to Cryogenic Temperatures

Résumé

Thermal effects are a major concern for efficient cryoCMOS circuit design. This work presents an experimental analysis of self-heating effect and thermal propagation in FD-SOI technology, measured from room temperature (300K) down to 4.2K, using the gate resistance thermometry technique. The channel temperature increase and the in-plane temperature profile were investigated and analytically modeled, together with thermal coupling between simultaneously operating devices. We demonstrated a major constraint for extremely low temperature operation due to abrupt channel temperature rise even at sub-1mW input power, which propagates over hundreds of nanometers along the Si layer. Thermal coupling was identified as a source for self-heating aggravation, and needs to be particularly optimized to limit the heating of cryo-circuits.
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cea-04524929 , version 1 (28-03-2024)

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Flavio-Enrico Bergamaschi, Tadeu Mota Frutuoso, Bruna Cardoso Paz, Louis Jansen, Philippe Galy, et al.. Experimental Analysis and Modeling of Self-Heating and Thermal Coupling in 28 nm FD-SOI CMOS Transistors Down to Cryogenic Temperatures. IEEE Transactions on Electron Devices, 2024, 71 (4), pp.2598 - 2604. ⟨10.1109/TED.2024.3367316⟩. ⟨cea-04524929⟩
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