Performance and Design Considerations for Gate-All-Around Stacked-NanoWires FETs
Résumé
This paper presents recent progress on Gate-All-Around (GAA) stacked-NanoWire (NW) / NanoSheet (NS) MOSFETs. Key technological challenges will be discussed and recent research results presented. Width-dependent carrier mobility in Si NW/NS and FinFET will be analyzed, and intrinsic performance and design considerations of GAA structures will be discussed and compared to FinFET devices with a focus on electrostatics, parasitic capacitances and different layout options. The results show that more flexibility can be achieved with stacked-NS transistors in order to manage power-performance optimization.
Domaines
Sciences de l'ingénieur [physics]Origine | Fichiers produits par l'(les) auteur(s) |
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