Poster De Conférence Année : 2024

Simplified cradle to gate Life Cycle Assessment of SiC transistor fabrication

Résumé

Due to human activities, Earth is facing increasing environmental issues, seriously affecting life and human living conditions (drought, flood, extreme events…). The European Green Deal with its net zero ambition in 2050, along with several regulations (GHG report obligation, CSRD, circular economy action plan, raw material act..) hopes to mitigate them [1]. At the same time, to keep in the race of technology innovation, European Union launched the European Chips Act to strengthen its technological leadership in the semiconductor field and ensure its sovereignty [2]. This second ambition must be tackled along with the first one, meaning that for any new technology in development, sustainability studies must be performed as early as possible to co-optimize performance AND sustainability. Rapid and massive electrification ongoing to reduce human activity effects on climate change implies an exponential increase of power electronic devices. Silicon based power devices are progressively replaced by wide band gap devices to benefit from their improved conversion yields and power density. However, few studies evaluate the global environmental impacts of these new technologies during their full life cycle. Power electronics sustainability studies generally take into account only the ‘use phase’ and report mainly on CO2 eq emission related to electricity use [3]. This work evaluates environmental impacts of SiC transistor fabrication following a simplified cradle to gate Life Cycle Assessment (LCA) methodology. The fabrication flow is divided in 3 sub-steps ‘SiC substrate’, ‘SiC wafer process’ and ‘metallization’. The life cycle inventory of each sub-step will be detailed (data from literature [4] and ecoinvent database). Impact Assessment was performed using Simapro software, Ecoinvent database and the European Product Environmental Footprint (PEF) method. Different electricity mixes and various scenarios at ‘SiC substrate’ sub-step have been studied. Hot-spots will be presented along with paths to decrease environmental impacts. Limits and interests of this study will be discussed. Keywords: Life Cycle Assessment (LCA), Power Device, Silicon Carbide (SiC)
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Année Mois Jours
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vendredi 13 juin 2025
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vendredi 13 juin 2025
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Dates et versions

cea-04837740 , version 1 (13-12-2024)

Identifiants

  • HAL Id : cea-04837740 , version 1

Citer

Murielle Fayolle-Lecocq, Laura Vauche, Elise Chaumat. Simplified cradle to gate Life Cycle Assessment of SiC transistor fabrication. Symposium pour l’électronique et le numérique durables, Dec 2024, Grenoble, France. 2024. ⟨cea-04837740⟩
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