This work focusses on the modeling of the Phase Noise (PhN) through the building blocks of a high-order-N frequency multiplication circuit that uses Pulsed injection Locking Oscillator (P-OSC). The proposed analytical expressions allow predicting the transformation of PhN through different blocks of the frequency multiplier. To cope with the inherent nonlinear characteristics of frequency multiplication circuits, simplified nonlinear equivalent circuits (NEC) are used to loosen the time and memory constraints of the numerical simulations. The analytical results show good agreements with Harmonic Balance simulations of NEC. This work helps determining the circuit key parameters controlling Phase Noise and output integrated RMS Jitter for optimization purposes.