Sub-6GHz SOI-CMOS High-Efficiency Linear PA Architectures: Challenges, Technics and Opportunities
Abstract
The need to provide secure and reliable remote access to vast amounts of data to a large number of users – people but also smart things – has prompted the emergence and fast adoption of 5G, Wi-Fi 6, Bluetooth 5, UWB and several other wireless protocols. Compared to legacy systems, modern user equipment (UE) - using the above listed protocols – rely on RF signals with ever increasing waveform complexity (increasing modulation order). Such signals are transmitted and received over larger bandwidths in new or refarmed frequency spectrum bands going from some MHz to potentially 100s of GHz. All of these while consuming less power and with minimum or no user equipment form factor changes.
Modern UE RF and mmWave Front Ends (RFFE) semiconductor technologies must therefore meet stringent linearity, power efficiency, monolithic and/or module dense integration and other requirements.
This workshop will provide guidelines on the use of performance and supply proven CMOS on RF-SOI to implement comprehensive RF and mmWave Front-End (RFFE) design and manufacturing methodologies. It will also provide an overview of other complementary RFFE semiconductor technologies needed to ensure system level performance.