Article Dans Une Revue ECS Transactions Année : 2022

Vertical GeSn/Ge heterostructure gate-all-around nanowire p-MOSFETs

Résumé

A process for the fabrication of vertical gate-all-around (GAA) nanowire p-FETs with diameters of down to 20 nm based on Ge and GeSn/Ge-heterostructures is presented. The resulting Ge-based devices exhibit a low subthreshold slope (SS) of 66 mV/dec, a low drain-induced barrier lowering of 35 mV/V and an I on / I off -ratio of 2.1×10 6 for devices with a diameter of 20 nm. Using a GeSn/Ge-heterostructure with GeSn as the top layer and source of the device, the on-current was increased by ~32%. With these results the high potential of incorporation of GeSn into Ge-MOSFET technology is demonstrated.
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Dates et versions

cea-04793546 , version 1 (20-11-2024)

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Yannik Junk, Mingshan Liu, Marvin Frauenrath, Jean-Michel Hartmann, Detlev Gruetzmacher, et al.. Vertical GeSn/Ge heterostructure gate-all-around nanowire p-MOSFETs. ECS Transactions, 2022, 108 (5), pp.83-91. ⟨10.1149/10805.0083ecst⟩. ⟨cea-04793546⟩
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