Effective InAsP dislocation filtering layers for InP heteroepitaxy on CMOS-standard (001) silicon - CEA - Commissariat à l’énergie atomique et aux énergies alternatives
Article Dans Une Revue Applied Physics Letters Année : 2024

Effective InAsP dislocation filtering layers for InP heteroepitaxy on CMOS-standard (001) silicon

Résumé

In this work, we report InAsP-based dislocation filter layers (DFLs) for InP heteroepitaxy on CMOS-standard (001) Si substrates, demonstrating a threading dislocation density of 3.7 107 cm2. The strain introduced by InAsP induces dislocation bending at the InAsP/InP interface, thereby facilitating the reaction and annihilation of dislocations during their lateral glide. Concurrently, the InP spacer exhibits tensile strain, leading to the formation of stacking faults (SFs). With a comprehensive analysis utilizing x-ray diffraction, electron channeling contrast imaging, and transmission electron microscopy, the effects of DFL-induced strain on dislocations and SFs are investigated. Finetuning the strain conditions allowed low-dislocation-density while SF-suppressed, anti-phase boundary free InP on Si. This work, therefore, provides a useful buffer engineering scheme for monolithic integration of InP-based electronic and photonic devices onto the industrystandard silicon platform.
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cea-04767437 , version 1 (05-11-2024)

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Shangfeng Liu, Bogdan-Petrin Ratiu, Hui Jia, Zhao Yan, Ka Ming Wong, et al.. Effective InAsP dislocation filtering layers for InP heteroepitaxy on CMOS-standard (001) silicon. Applied Physics Letters, 2024, 125, pp.082102. ⟨10.1063/5.0219507⟩. ⟨cea-04767437⟩
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