Communication Dans Un Congrès Année : 2024

Low Resistance and High Isolation HD TSV for 3-Layer CMOS Image Sensors

Résumé

We developed 1x6μm copper TSV with improved performances in terms of electrical resistance and isolation compared to our formerly published 1x10 μm HD TSV. This was possible thanks to an optimized thinning process that enabled us reducing the substrate thickness down to 5 μm with a good uniformity. This shortening of the TSV allowed a decrease of their resistance and an increase of their voltage withstand. We implemented such TSV in a 2L demonstrator that we characterized morphologically and electrically. The connection yield through hybrid bonding and TSV reached 100 %. At the same time, we used a simpler 1L test vehicle to go further in the optimization of the TSV by upgrading the materials and processes for even higher performances.

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Dates et versions

cea-04758563 , version 1 (29-10-2024)

Identifiants

Citer

Stéphan Borel, Myriam Assous, Rémi Vélard, Jerzy-Javier Suarez-Berru, Stéphane Nicolas, et al.. Low Resistance and High Isolation HD TSV for 3-Layer CMOS Image Sensors. 2024 IEEE 74th Electronic Components and Technology Conference (ECTC), May 2024, Denver, United States. pp.771-777, ⟨10.1109/ECTC51529.2024.00126⟩. ⟨cea-04758563⟩
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