Body resistance model for Partially Depleted SOI device: charge-based approach, extraction and Verilog-A implementation - CEA - Commissariat à l’énergie atomique et aux énergies alternatives
Conference Papers Year : 2023

Body resistance model for Partially Depleted SOI device: charge-based approach, extraction and Verilog-A implementation

Abstract

The Partially Depleted Silicon On Insulator (PDSOI) transistor is used for a wide range of applications, in particular for RF. The current standard compact model of SOI-like transistor does not take into account a bias dependence of the body resistance. Building upon our experience developing the PSP model, we propose here a stand-alone Verilog-A model of body resistance. This nonlinear resistance model is validated against 3D TCAD and 65nm PDSOI experimental data.
No file

Dates and versions

cea-04752138 , version 1 (24-10-2024)

Identifiers

Cite

Sébastien Martinie, Adrien Vaysset, Yannick Mourrier, Patrick Scheer, Olivier Rozeau. Body resistance model for Partially Depleted SOI device: charge-based approach, extraction and Verilog-A implementation. 2023 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Sep 2023, Kobe, Japan. pp.129-132, ⟨10.23919/SISPAD57422.2023.10319516⟩. ⟨cea-04752138⟩
0 View
0 Download

Altmetric

Share

More