Electrical characterization of 200 mm 4H-SiC-on-polycristalline SiC wafers bonding interface
Résumé
In the context of a rapid increase of 4H-SiC based power devices usage, while this industry is facing a global shortage of wafers, engineered substrates processed using the ion cutting Smart CutTM technology can offer key advantages [1]. These substrates were fabricated by transferring a thin layer from a high-quality monocrystalline wafer onto a cheaper, more available, low resistivity polycrystalline handle substrate. The expensive donor substrate can then be reused to fabricate multiple engineered substrates, using the appropriate surface preparation. In addition to cost cutting and volume production improvements, polycrystalline SiC (poly-SiC) substrates typically possess a resistivity one order of magnitude lower than monocrystalline highly doped n-type 4H-SiC. Besides significantly reducing the device access resistance, this opens new flexible ways of processing the backside for ohmic contact fabrication. A previous work reported that the typical silicide layer, demanding a high thermal budget annealing [2], is not required to obtain an excellent contact resistance on poly-SiC [3, 4]. However, to take full advantage of this technology, it is critical that the bonding interface resistivity remains low. In this work, we will propose a general methodology to extract the bonding interface resistivity, with a relatively easy to process test vehicle based on a lateral design.