Communication Dans Un Congrès Année : 2020

Cyclic scheduling of loop-intensive applications on heterogeneous multiprocessor architectures

Résumé

This paper tackles the scheduling of loop-intensive applications modeled by synchronous dataflow graphs (SDFGs) on heterogeneous multiprocessor architectures under resource and communication constraints. Scheduling an application graph on multiprocessor architectures under resource constraints is a well-known NP•hard problem widely addressed in the previous decades with the goal of optimizing different performance metrics such as latency, memory allocations, energy consumption, throughput, etc. In this paper, we focus on the study of cyclic scheduling strategies and specifically the software pipelined schedules of SDFGs under the resource and communication constraints of heterogeneous multiprocessor architectures and we made two major contributions. The first contribution is an integer linear programming (ILP) model for the exact resolution of the scheduling problem and the second contribution is a time-efficient heuristic that generates scheduling solutions close to the optimal solutions generated with our ILP model. Index Tenns-Cyclic scheduling, software pipelining, synchronous dataflow graphs, heterogeneous multiprocessor architectures, throughput, cyber-physical systems.
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Dates et versions

cea-04485112 , version 1 (01-03-2024)

Identifiants

Citer

Philippe Glanon, Selma Azaiez, Chokri Mraidha. Cyclic scheduling of loop-intensive applications on heterogeneous multiprocessor architectures. RTCSA 2020 - IEEE 26th International Conference on Embedded and Real-Time Computing Systems and Applications, Aug 2020, On line event, South Korea. pp.1-10, ⟨10.1109/RTCSA50079.2020.9203667⟩. ⟨cea-04485112⟩
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