Sub-pJ consumption and short latency time in RRAM arrays for high endurance applications
Abstract
In this paper, programming operations are optimized
for low energy consumption and short latency time applications
in RRAM kb arrays. Origin of consumption (role of pulse’s
time, programming current and voltage in SET and RESET
operations) is quantified on HfO$_2$ oxide based RRAM
technology. Specific patterns are evaluated to reduce latency
time and energy consumption in memory devices. Innovative
circuit with $on\ the\ fly$ switching detection is proposed, allowing
to reduce programming consumption down to single pJ
operation in large memory arrays.