Reducing power with activity trigger analysis
Résumé
In this paper we propose and implement a methodology for power reduction in digital circuits, closing the gap between conceptual (by designer) and local (by EDA) clock gating. We introduce a new class of coarse grained local clock gating conditions and develop a method for detecting such conditions and formally proving their correctness. The detection of these conditions relies on architecture characterization and statistical analysis of simulation, all done at the RTL. Formal verification is performed on an abstract circuit model. We demonstrate a significant power reduction from 33 to 40% of total power on a clusterized circuit design for video processing.
Mots clés
Video signal processing
Analysis of simulations
Circuit designs
Circuit modeling
Integrated circuit modeling
Power demands
Power reductions
Registers
Video processing
Formal methods
Analytical models
Circuit simulation
Clocks
Computers
Integrated circuit manufacture
Reconfigurable hardware
Statistical methods