P-type Extended Drain MOSFET integration on thin SOI - CEA - Commissariat à l’énergie atomique et aux énergies alternatives
Communication Dans Un Congrès Année : 2024

P-type Extended Drain MOSFET integration on thin SOI

Résumé

In this paper, we demonstrate for the first time the functionality of a P-type eDMOS on thin Silicon-On- Insulator (SOI, 23nm Si-25nm BOX), with breakdown voltage BV=17V, RONxS=5.9 mΩ.mm², and IOFF=2pA/μm at VDS=-7V. The 23nm Si film is sufficiently thick to enable high BV while also being thin enough to allow flexibility through the back-gate and to restrict Floating Body effects. In order to address specific application requirements, the breakdown voltage and ONresistance (BV, RON) tradeoffs can be optimized with the extension doping and length, as well as the back-gate bias. These results demonstrate the feasibility of SOI P-eDMOS cointegration with thin SOI CMOS technologies for highvoltage and high-power applications such as DC-DC converters for power management.
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Dates et versions

cea-04749068 , version 1 (22-10-2024)

Identifiants

  • HAL Id : cea-04749068 , version 1

Citer

Ayoub Boutayeb, Dominique Golanski, Christoforos Theodorou, François Guyader, Sylvain Joblot, et al.. P-type Extended Drain MOSFET integration on thin SOI. ESSERC 2024, Sep 2024, bruges, Belgium. pp.9-12. ⟨cea-04749068⟩
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