P-type Extended Drain MOSFET integration on thin SOI
Abstract
In this paper, we demonstrate for the first time
the functionality of a P-type eDMOS on thin Silicon-On-
Insulator (SOI, 23nm Si-25nm BOX), with breakdown voltage
BV=17V, RONxS=5.9 mΩ.mm², and IOFF=2pA/μm at VDS=-7V.
The 23nm Si film is sufficiently thick to enable high BV while
also being thin enough to allow flexibility through the back-gate
and to restrict Floating Body effects. In order to address specific
application requirements, the breakdown voltage and ONresistance
(BV, RON) tradeoffs can be optimized with the
extension doping and length, as well as the back-gate bias. These
results demonstrate the feasibility of SOI P-eDMOS
cointegration with thin SOI CMOS technologies for highvoltage
and high-power applications such as DC-DC converters
for power management.