Process Variability—Technological Challenge and Design Issue for Nanoscale Devices - CEA - Commissariat à l’énergie atomique et aux énergies alternatives Access content directly
Journal Articles Micromachines Year : 2019

Process Variability—Technological Challenge and Design Issue for Nanoscale Devices

Abstract

Current advanced transistor architectures, such as FinFETs and (stacked) nanowires and nanosheets, employ truly three-dimensional architectures. Already for aggressively scaled bulk transistors, both statistical and systematic process variations have critically influenced device and circuit performance. Three-dimensional device architectures make the control and optimization of the device geometries even more important, both in view of the nominal electrical performance to be achieved and its variations. In turn, it is essential to accurately simulate the device geometry and its impact on the device properties, including the effect caused by non-idealized processes which are subject to various kinds of systematic variations induced by process equipment. In this paper, the hierarchical simulation system developed in the SUPERAID7 project to study the impact of variations from equipment to circuit level is presented. The software system consists of a combination of existing commercial and newly developed tools. As the paper focuses on technological challenges, especially issues resulting from the structuring processes needed to generate the three-dimensional device architectures are discussed. The feasibility of a full simulation of the impact of relevant systematic and stochastic variations on advanced devices and circuits is demonstrated.
Fichier principal
Vignette du fichier
Lor11.pdf (5.58 Mo) Télécharger le fichier
Origin Publisher files allowed on an open archive
Loading...

Dates and versions

cea-02965982 , version 1 (13-10-2020)

Licence

Identifiers

Cite

Jürgen Lorenz, Eberhard Bär, Sylvain Barraud, Andrew R. Brown, Peter Evanschitzky, et al.. Process Variability—Technological Challenge and Design Issue for Nanoscale Devices. Micromachines, 2019, 10 (1), pp.6. ⟨10.3390/mi10010006⟩. ⟨cea-02965982⟩
362 View
47 Download

Altmetric

Share

Gmail Mastodon Facebook X LinkedIn More