Stacked-Wires FETs for advanced CMOS scaling
Abstract
We present recent progress on vertically stacked-wires MOSFETs with a replacement metal gate process for CMOS scaling beyond FinFET technology. Key technological challenges (such as 3D integration process including inner spacer, mobility, and strain engineering) will be discussed in relation to recent research results.
Domains
Engineering Sciences [physics]Origin | Files produced by the author(s) |
---|
Loading...