Reading reliability in 1S1R OTS+PCM devices based on Double-Patterned Self-Aligned structure
Résumé
This study investigates the reliability of the reading operation in 1S1R devices based on Ovonic Threshold Switching (OTS) selector and Phase-Change Memory (PCM) co-integrated in a Double-Patterned Self-Aligned (DPSA) structure targeting Crossbar applications. Upon reading, the SET state can face a threshold voltage (Vth) increase of more than 20% dependently on the reading current and on the number of reading operations, which can lead to a soft failure. We separate the contributions to this increase coming respectively from OTS and PCM, finally providing an assessment protocol for the reading reliability. We show how the reading performances allow to determine the maximum Crossbar array size depending on the target voltage Read Window Margin and current Memory Window.
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