Computational SRAM Design Automation using Pushed-Rule Bitcells for Energy-Efficient Vector Processing
J.-P Noel
,
Valentin Egloff
,
M. Kooli
,
R. Gauchi
,
J.-M. Portal
,
et al.
Conference papers
cea-02889406v1
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Memory Sizing of a Scalable SRAM In-Memory Computing Tile Based Architecture
R Gauchi
,
M Kooli
,
P Vivet
,
J.-P Noel
,
E. Beigné
,
et al.
IFIP/IEEE International Conference on Very Large Scale Integration and System-on-Chip (VLSI-SoC) , Oct 2019, Cuzco, Peru
Conference papers
cea-02399937v1
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Reconfigurable tiles of computing-in-memory SRAM architecture for scalable vectorization
Roman Gauchi
,
Valentin Egloff
,
Maha Kooli
,
Jean-Philippe Noel
,
Bastien Giraud
,
et al.
ISLPED 2020: ACM/IEEE International Symposium on Low Power Electronics and Design , Aug 2020, Boston, MA, United States. pp.121-126,
⟨10.1145/3370748.3406550⟩
Conference papers
cea-02963719v1
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A 35.6TOPS/W/mm$^2$ 3-Stage Pipelined Computational SRAM with Adjustable Form Factor for Highly Data-Centric Applications
J.-P Noel
,
M. Pezzin
,
R. Gauchi
,
J.-F Christmann
,
M. Kooli
,
et al.
Journal articles
cea-02904882v1
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