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authIdHal_s : cfuguet

A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm 2 Inter-Chiplet Interconnects and 156mW/mm 2 @ 82%-Peak-Efficiency DC-DC Converters

Pascal Vivet , Eric Guthmuller , Yvain Thonnart , Gaël Pillonnet , Guillaume Moritz , et al.
2020 IEEE International Solid- State Circuits Conference - (ISSCC), Feb 2020, San Francisco, United States. pp.46-48, ⟨10.1109/ISSCC19947.2020.9062927⟩
Conference papers hal-02985945v1

Trace-driven exploration of sharing set management strategies for cache coherence in manycores

J. Dumas , E. Guthmuller , C. Fuguet Tortolero , Frédéric Pétrot
15th IEEE International New Circuits and Systems Conference (NEWCAS'17), Jun 2017, Strasbourg, France. pp.77-80
Conference papers hal-01701046v1
Image document

HPDcache: Open-source high-performance L1 data cache for RISC-V cores

César Fuguet
20th ACM International Conference on Computing Frontiers, May 2023, Bologne, Italy. pp.385, ⟨10.1145/3587135.3591413⟩
Conference papers cea-04110679v1
Image document

Storage class memory with computing row buffer: A design space exploration

Valentin Egloff , Jean-Philippe Noel , Maha Kooli , Bastien Giraud , Lorenzo Ciampolini , et al.
Other publications cea-03605068v1

128-bit addresses for the masses (of memory and devices)

Mathieu Bacou , Adam Chader , Chandana S. Deshpande , Christian Fabre , César Fuguet , et al.
HotInfra 2023 - Workshop on Hot Topics in System Infrastructure, Jun 2023, Orlando, United States. 2023
Conference poster hal-04161640v1
Image document

IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management

Pascal Vivet , Eric Guthmuller , Yvain Thonnart , Gaël Pillonnet , Cesar Fuguet , et al.
IEEE Journal of Solid-State Circuits, 2021, 56 (1), pp.79-97. ⟨10.1109/JSSC.2020.3036341⟩
Journal articles hal-03072959v1

ExaNoDe: Combined Integration of Chiplets on Active Interposer with Bare Dice in a Multi-Chip-Module for Heterogeneous and Scalable High Performance Compute Nodes

P. Martinez , Y. Beilliard , M. Godard , D. Danovitch , D. Drouin , et al.
2020 IEEE Symposium on VLSI Technology, Jun 2020, Honolulu, IEEE, pp.1-2, 2020, ⟨10.1109/VLSITechnology18217.2020.9265100⟩
Proceedings hal-03178715v1
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POPSTAR: a robust modular optical NoC architecture for chiplet-based 3D integrated systems

Yvain Thonnart , Stephane Bernabe , Jean Charbonnier , Christian Bernard , David Coriat , et al.
DATE 2020 - Design, Automation & Test in Europe Conference & Exhibition, Mar 2020, Grenoble, France. pp.1456-1461, ⟨10.23919/DATE48585.2020.9116214⟩
Conference papers cea-03471376v1

We had 64-bit, yes. What about second 64-bit?

Mathieu Bacou , Adam Chader , Chandana S. Deshpande , Christian Fabre , César Fuguet , et al.
RISC-V Summit Europe 2023, Jun 2023, Barcelona, Spain. 2023
Conference poster hal-04161612v1

A Method for Fast Evaluation of Sharing Set Management Strategies in Cache Coherence Protocols

J. Dumas , E. Guthmuller , C. Fuguet Tortolero , Frédéric Pétrot
30th International Conference on Architecture of Computing Systems (ARCS 2017), Apr 2017, Vienna, Austria. pp.111-123
Conference papers hal-01523232v1