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CMOS-compatible manufacturability of sub-15 nm Si/SiO$_2$/Si nanopillars containing single Si nanodots for single electron transistor applicationsSemiconductor Science and Technology, 2023, 38 (5), pp.055011. ⟨10.1088/1361-6641/acbe5d⟩
Journal articles
cea-04170374v1
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Sub-20 nm multilayer nanopillar patterning for hybrid SET/CMOS integrationMicro and Nano Engineering, 2020, 9, https://doi.org/10.1016/j.mne.2020.100074. ⟨10.1016/j.mne.2020.100074⟩
Journal articles
cea-03409432v1
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CMOS compatible manufacturing of a hybrid SET-FET circuitJournal of Semiconductor Science and Technology, 2022, 37, pp.125014. ⟨10.1088/1361-6641/ac9f61⟩
Journal articles
cea-04174052v1
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