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Computational SRAM Design Automation using Pushed-Rule Bitcells for Energy-Efficient Vector Processing2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), Mar 2020, Grenoble, France. pp.1187-1192, ⟨10.23919/DATE48585.2020.9116506⟩
Conference papers
cea-02889406v1
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Memory Sizing of a Scalable SRAM In-Memory Computing Tile Based ArchitectureIFIP/IEEE International Conference on Very Large Scale Integration and System-on-Chip (VLSI-SoC), Oct 2019, Cuzco, Peru
Conference papers
cea-02399937v1
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A 35.6TOPS/W/mm$^2$ 3-Stage Pipelined Computational SRAM with Adjustable Form Factor for Highly Data-Centric ApplicationsIEEE Solid-State Circuits Letters, 2020, ⟨10.1109/LSSC.2020.3010377⟩
Journal articles
cea-02904882v1
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