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Layered LDPC Decoders With Efficient Memory Access Scheduling and Mapping and Built-In Support for Pipeline Hazards MitigationIEEE Transactions on Circuits and Systems I: Regular Papers, 2019, 66 (4), pp.1643-1656. ⟨10.1109/TCSI.2018.2884252⟩
Journal articles
cea-02186481v1
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