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On Line Power Optimization of Data Flow Multi-core Architecture Based on Vdd-Hopping for Local DVFS20th IEEE International Workshop d Timing Modeling, Optimization and Simulation (PATMOS'10), Sep 2010, Grenoble, France
Conference papers
hal-01445862v1
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On Line Power Optimization of Data Flow Multi-core Architecture Based on Vdd-Hopping for Local DVFSIntegrated Circuit and System Design, springer pp.94-104, 2011, 978-3-642-17751-4
Book sections
hal-01529251v1
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Memory Sizing of a Scalable SRAM In-Memory Computing Tile Based ArchitectureIFIP/IEEE International Conference on Very Large Scale Integration and System-on-Chip (VLSI-SoC), Oct 2019, Cuzco, Peru
Conference papers
cea-02399937v1
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On-line Power Optimization of Data Flow Multi-Core Architecture Based on Vdd-Hopping for Local Dynamic Voltage and Frequency ScalingJournal of Low Power Electronics, 2011, 7 (2), pp.265-273. ⟨10.1166/jolpe.2011.1135⟩
Journal articles
hal-01142565v1
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DPA on quasi delay insensitive asynchronous circuits: concrete resultsXIX Conference on Design of Circuits and Integrated Systems (DCIS'04), Nov 2004, Bordeaux, France
Conference papers
hal-01399172v1
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