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authFullName_s : C. Le Royer

Characterization of impact of process options in Germanium-On-Insulator (GeOI) high-k & metal gate pMOSFETs by low-frequency noise

M. Valenza , J. Gyani , F. Martinez , S. Soliverès , C. Le Royer , et al.
Solid-State Electronics, 2011, 59 (1), pp.34 - 38. ⟨10.1016/j.sse.2011.01.015⟩
Journal articles istex hal-01653011v1

Impact Of Single Charge Trapping On The Variability of Ultra-Scaled Planar And Tri-Gate FDSOI MOSFETs: Experiment vs Simulation

A. Subirats , X. Garros , J. El Husseini , C. Le Royer , G. Reimbold , et al.
IEEE Transactions on Electron Devices, 2013, 60, pp.2604-2610
Journal articles hal-01018674v1

Selected SOI puzzles and tentative answers

K.-I. Na , W. van den Daele , L. Pham-Nguyen , M. Bawedin , K.-H. Park , et al.
1st Ukrainian-French Symposium 'Semiconductor-On-Insulator Materials, Devices and Circuits: Physics, Technology and Diagnostics, Oct 2010, Kiev, Ukraine
Conference papers hal-00604923v1

New numerical low frequency noise model for front and buried oxide trap density characterization in FDSOI MOSFETs

J. El Husseini , Frédéric Martinez , J. Armand , M. Bawedin , M. Valenza , et al.
Microelectronic Engineering, 2011, 88 (7), pp.1286-1290. ⟨10.1016/j.mee.2011.03.095⟩
Journal articles istex hal-02093037v1

First SOI Tunnel FETs with low-temperature process

C. Diaz Llorente , C. Le Royer , C-M. Lu , P. Batude , C. Fenouillet-Beranger , et al.
2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Apr 2017, Athens, Greece. pp.9-12, ⟨10.1109/ULIS.2017.7962579⟩
Conference papers hal-02007188v1

Gate-last integration on planar FDSOI for low-VTp and low-EOT MOSFETs

S. Morvan , F. Andrieu , Cédric Leroux , X. Garros , M. Casse , et al.
Microelectronic Engineering, 2013, 109, pp.306-309. ⟨10.1016/j.mee.2013.03.045⟩
Journal articles hal-00996453v1

Experimental Investigation of the Tunneling Injection Boosters for Enhanced ION ETSOI Tunnel FET

A. Villalon , C. Le Royer , M. Casse , D. Cooper , J.-M. Hartmann , et al.
IEEE Transactions on Electron Devices, 2013, 60 (12), pp.4079-4084. ⟨10.1109/TED.2013.2287610⟩
Journal articles hal-00994546v1

On the use of a localized STRASS technique to obtain highly tensile strained Si regions in advanced FDSOI CMOS devices

A. Bonnevialle , S. Reboh , C. Le Royer , Y. Morand , J.-M. Hartmann , et al.
physica status solidi (c), 2016, 13 (10-12), pp.740-745. ⟨10.1002/pssc.201600028⟩
Journal articles istex hal-01719490v1

Review of some critical aspects of Ge and GeOI substrates

L. Clavelier , C. Deguet , C. Le Royer , B. Vincent , J.-F. Damlencourt , et al.
Workshop on Germanium for CMOS, Nov 2006, ville indéterminée, Unknown Region. pp.789-805, ⟨10.1149/1.2355874⟩
Conference papers hal-01736072v1
Image document

New prospects on high on-current and steep subthreshold slope for innovative Tunnel FET architectures

C. Diaz Llorente , J.-P. Colinge , S. Martinie , S. Cristoloveanu , J. Wan , et al.
Solid-State Electronics, 2019, 159, pp.26-37. ⟨10.1016/j.sse.2019.03.046⟩
Journal articles hal-02321885v1

(Invited) Special Memory Mechanisms in SOI Devices

S. Cristoloveanu , M. Bawedin , C. Navarro , S. Chang , J. Wan , et al.
227th ECS Meeting: 17th Int. Symposium on Advanced CMOS-Compatible Semiconductor Devices, Y. Omura, J.A. Martino, J.P. Raskin, S. Selberherr, H. Ishi, F. Gamiz and B. Nguye, May 2015, Chigaco, United States
Conference papers hal-02007799v1

Mechanical simulation of stress engineering solutions in highly strained p-type FDSOI MOSFETs for 14-nm node and beyond

A. Idrissi-El Oudrhiri , S. Martinie , J-C. Barbe , O. Rozeau , C. Le Royer , et al.
2015 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Sep 2015, Washington DC, United States. pp.206-209, ⟨10.1109/SISPAD.2015.7292295⟩
Conference papers hal-02016552v1

A comparative 1/f noise study of GeOI wafers obtained by the Ge enrichment technique and the Smart Cut technology

M. Valenza , J. El Husseini , J. Gyani , Frédéric Martinez , M. Bawedin , et al.
Microelectronic Engineering, 2011, 88 (7), pp.1298-1300. ⟨10.1016/j.mee.2011.03.090⟩
Journal articles istex hal-02064898v1

Ion-Ioff performance analysis of FDSOI MOSFETs with low processing temperature

Cuiqin Xu , P. Batude , C. Rauer , C. Le Royer , L. Hutin , et al.
Solid-State Devices Meeting, Sep 2010, tokyo, Japan
Conference papers hal-00604646v1

Low-temperature measurements on Germanium-on-Insulator pMOSFETs: evaluation of the background doping level

W. van den Daele , E. Augendre , S. Cristoloveanu , C. Le Royer , L. Clavelier , et al.
Proc. in Silicon-on-Insulator Technology and Devices 14, (Y. Omura, S. Cristoloveanu, F. Gamiz, B-Y. Nguyen eds.), Pennington (USA), ECS Transactions, in press (2009, May 2009, San Francisco, United States
Conference papers hal-00603712v1

Self-aligned contacts for 10nm FDSOI node : from device to circuit evaluation

H. Niebojewski , C. Le Royer , Y. Morand , O. Rozeau , M.A. Jaud , et al.
39th IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, IEEE S3S 2013, 2013, Monterey, CA, United States. paper 6a.4, 2 p., ⟨10.1109/S3S.2013.6716549⟩
Conference papers hal-00955675v1

Low Temperature Characterization of Hole Mobility in Sub-14nm Gate Length Si 0.7 Ge 0.3 Tri-Gate pMOSFETs

R. Lavieville , C. Le Royer , S. Barraud , G. Ghibaudo
12th International Workshop on Low Temperature Electronics (WOLTE-12), Sep 2016, Tempe, United States
Conference papers hal-02072793v1

Beyond TFET: Alternative mechanisms for CMOS-compatible sharp-switching devices

S. Cristoloveanu , J. Wan , P. Ferrari , M. Bawedin , C. Navarro , et al.
2014 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Oct 2014, Millbrae, United States. pp.5.12, ⟨10.1109/S3S.2014.7028228⟩
Conference papers hal-02003987v1

Experimental investigations of SiGe channels for enhancing the SGOI tunnel FETs performance

C. Le Royer , A. Villalon , S. Martinie , P. Nguyen , S. Barraud , et al.
2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Jan 2015, Bologna, Italy. pp.69-72, ⟨10.1109/ULIS.2015.7063775⟩
Conference papers hal-02004064v1

1∕f noise in 0.12 μm P-MOSFETs with High-k and metal gate fabricated in a Si Process Line on 200 mm GeOI Wafers

J. Gyani , Frédéric Martinez , S. Soliverès , M. Valenza , C. Le Royer , et al.
NOISE AND FLUCTUATIONS: 20th International Conference on Noice and Fluctuations (ICNF-2009), 2009, Pisa (Italy), Italy. pp.259-262, ⟨10.1063/1.3140445⟩
Conference papers hal-02063016v1

Improved extraction of GIDL in FDSOI devices for proper junction quality analysis

C. Xu , P. Batude , K. Romanjek , C. Le Royer , C. Tabone , et al.
2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC), Sep 2011, Helsinki, Finland. ⟨10.1109/ESSDERC.2011.6044183⟩
Conference papers hal-01959402v1

Extra-low parasitic gate-to-contacts capacitance architecture for sub-14 nm transistor nodes

Heimanu Niebojewski , C. Le Royer , Y. Morand , O. Rozeau , M.A. Jaud , et al.
Solid-State Electronics, 2014, 97, pp.45-51. ⟨10.1016/j.sse.2014.04.028⟩
Journal articles hal-01000014v1

Sharp-Switching CMOS-Compatible Devices with High Current Drive

J. Wan , S. Cristoloveanu , S. T. Le , A. Zaslavsky , C. Le Royer , et al.
Serge Luryi,Jimmy Xu and Alex Zaslavsky. Future Trends in Microelectronics: Frontiers and Innovations, John Wiley & Sons, Inc., Hoboken, NJ, USA, pp.81-92, 2013, 978-111-8442-16-6 (print)/978-1118678107(online). ⟨10.1002/9781118678107.ch5⟩
Book sections hal-01060432v1

(Invited) Special Memory Mechanisms in SOI Devices

S. Cristoloveanu , M. Bawedin , C. Navarro , S. Chang , J. Wan , et al.
ECS Transactions, 2015, Advanced CMOS-Compatible Semiconductor Devices 17, 66 (5), pp.201-210. ⟨10.1149/06605.0201ecst⟩
Journal articles hal-02007772v1

A review of the Z 2 -FET 1T-DRAM memory: Operation mechanisms and key parameters

S. Cristoloveanu , K.H. Lee , S. Parihar , H. El Dirani , J. Lacord , et al.
Solid-State Electronics, 2018, 143, pp.10-19. ⟨10.1016/j.sse.2017.11.012⟩
Journal articles hal-02003277v1

Impact of strain on access resistance in planar and nanowire CMOS devices

Rémy Berthelon , F. Andneu , F. Triozon , M. Cassé , L. Bourdet , et al.
2017 IEEE Symposium on VLSI Technology, Jun 2017, Kyoto, Japan. pp.T224-T225, ⟨10.23919/VLSIT.2017.7998180⟩
Conference papers hal-02050220v1
Image document

Accurate statistical extraction of AlGaN/GaN HEMT device parameters using the Y-function

R. Kom Kammeugne , C. Leroux , J. Cluzel , L. Vauche , C. Le Royer , et al.
Solid-State Electronics, 2021, 184, pp.108078. ⟨10.1016/j.sse.2021.108078⟩
Journal articles cea-03250807v1

Advanced pMOSFET on germanium-on-insulator : low temperature properties.

W. van den Daele , S. Cristoloveanu , E. Augendre , C. Le Royer , L. Clavelier , et al.
5th EUROSOI Workshop, Jan 2009, France. pp.1408-1411
Conference papers hal-00603743v1

Smart solutions for efficient dual strain integration for future FDSOI generations

A. Bonnevialle , C. Le Royer , Y. Morand , S. Reboh , C. Plantier , et al.
VLSI Technology, 2016 IEEE Symposium on, 2016, Unknown, Unknown Region. ⟨10.1109/VLSIT.2016.7573406⟩
Conference papers hal-01719489v1

High-Performance Ultrathin Body c-SiGe Channel FDSOI pMOSFETs Featuring SiGe Source and Drain: Vth Tuning, Variability, Access Resistance, and Mobility Issues

A. Villalon , C. Le Royer , S. Cristoloveanu , M. Casse , D. Cooper , et al.
IEEE Transactions on Electron Devices, 2013, 60 (5), pp.1568-1574. ⟨10.1109/TED.2013.2255055⟩
Journal articles hal-00994552v1