This work introduces an Open-Source, High-Performance, Out-of-Order (OoO), L1 Data Cache (HPDcache) compatible with RISC-V processor cores. As a case-study, this HPDcache was successfully integrated with the CVA6 core. A silicon implementation is being tapeout in the context of the European Processor Initiative (EPI) project and further improvements will be made on the context of the KDT Tristan project. The HPDcache SystemVerilog Register-Transfer Level (RTL) sources are contributed as open-source with permissive Solderpad v2.1 license. It is available through the OpenHW Github.