%0 Conference Paper %F Oral %T TiTe/Ge$_2$Sb$_2$Te$_5$ bi-layer-based Phase-Change Memory targeting storage class memory %+ Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI) %+ CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information %A Lama, G. %A Bernard, M. %A Garrione, J. %A Bernier, N. %A Castellani, N. %A Bourgeois, G. %A Cyrille, M.C. %A Andrieu, F. %A Navarro, Gabriele %< avec comité de lecture %B ESSDERC 2022 - IEEE 52nd European Solid-State Device Research Conference %C Milan, Italy %I IEEE %S ESSDERC 2022 - IEEE 52nd European Solid-State Device Research Conference (ESSDERC) %V 2022 %P 237-240 %8 2022-09-19 %D 2022 %R 10.1109/ESSDERC55479.2022.9947157 %Z Engineering Sciences [physics]Conference papers %X In this work, we introduce an innovative Phase-Change Memory (PCM) based on a TiTe and Ge$_2$Sb$_2$Te$_5$ (GST) bi-layer stack that presents low resistance variability since the out-of-fabrication in 4 kb array. It allows creating reliably an intermixed system right from the first programming in the active volume of the device. TiTe/GST PCM exhibits higher speed, lower variability of intermediate resistance states and lower drift compared to standard GST. An endurance of more than 10$^8$ cycles can be achieved and we found a reduced cycle-to-cycle variability even after endurance stress. Such new TiTe/GST stack, based on our results, demonstrates to be a valuable candidate for PCM targeting Storage Class Memory applications. %G English %2 https://cea.hal.science/cea-03927976/document %2 https://cea.hal.science/cea-03927976/file/GiusyLAMA_ESSDERC2022_v3_2.pdf %L cea-03927976 %U https://cea.hal.science/cea-03927976 %~ CEA %~ OPENAIRE %~ DRT %~ LETI %~ CEA-GRE