%0 Journal Article %T Sub-20 nm multilayer nanopillar patterning for hybrid SET/CMOS integration %+ Département Plate-Forme Technologique (DPFT) %+ Vistec Electron Beam GmbH %+ Helmholtz-Zentrum Dresden-Rossendorf (HZDR) %+ Fraunhofer Institute for Integrated Systems and Device Technology (Fraunhofer IISB) %A Pourteau, Marie-Line %A Gharbi, Ahmed %A Brianceau, Pierre %A Dallery, Jacques-Alexandre %A Laulagnet, Fabien %A Rademaker, Guido %A Tiron, Raluca %A Engelmann, Hans-Juergen %A von Borany, Johannes %A Heinig, Karl-Heinz %A Rommel, Mathias %A Baier, Leander %< avec comité de lecture %@ 2590-0072 %J Micro and Nano Engineering %I Elsevier %V 9 %P https://doi.org/10.1016/j.mne.2020.100074 %8 2020 %D 2020 %R 10.1016/j.mne.2020.100074 %K Single-electron-transistor %K Multilayer nanopillars %K Si nanodots %K E-beam lithography %K ICP-RIE %K EFTEM %Z Engineering Sciences [physics]/Micro and nanotechnologies/MicroelectronicsJournal articles %X SETs (Single-Electron-Transistors) arouse growing interest for their very low energy consumption. For future industrialization, it is crucial to show a CMOS-compatible fabrication of SETs, and a key prerequisite is the patterning of sub-20 nm Si Nano-Pillars (NP) with an embedded thin SiO2 layer. In this work, we report the patterning of such multi-layer isolated NP with e-beam lithography combined with a Reactive Ion Etching (RIE) process. The Critical Dimension (CD) uniformity and the robustness of the Process of Reference are evaluated. Characterization methods, either by CD-SEM for the CD, or by TEM cross-section for the NP profile, are compared and discussed. %G English %2 https://cea.hal.science/cea-03409432/document %2 https://cea.hal.science/cea-03409432/file/Sub-20%20nm%20multilayer%20nanopillar%20patterning%20for%20hybrid%20SETCMOS%20integration.pdf %L cea-03409432 %U https://cea.hal.science/cea-03409432 %~ CEA %~ OPENAIRE %~ DSV %~ DRT %~ CEA-DRF %~ LETI %~ CEA-GRE %~ MAP-CEA