@article{pourteau:cea-03409432, TITLE = {{Sub-20 nm multilayer nanopillar patterning for hybrid SET/CMOS integration}}, AUTHOR = {Pourteau, Marie-Line and Gharbi, Ahmed and Brianceau, Pierre and Dallery, Jacques-Alexandre and Laulagnet, Fabien and Rademaker, Guido and Tiron, Raluca and Engelmann, Hans-Juergen and von Borany, Johannes and Heinig, Karl-Heinz and Rommel, Mathias and Baier, Leander}, URL = {https://cea.hal.science/cea-03409432}, JOURNAL = {{Micro and Nano Engineering}}, PUBLISHER = {{Elsevier}}, VOLUME = {9}, PAGES = {https://doi.org/10.1016/j.mne.2020.100074}, YEAR = {2020}, DOI = {10.1016/j.mne.2020.100074}, KEYWORDS = {Single-electron-transistor ; Multilayer nanopillars ; Si nanodots ; E-beam lithography ; ICP-RIE ; EFTEM}, PDF = {https://cea.hal.science/cea-03409432/file/Sub-20%20nm%20multilayer%20nanopillar%20patterning%20for%20hybrid%20SETCMOS%20integration.pdf}, HAL_ID = {cea-03409432}, HAL_VERSION = {v1}, }