@inproceedings{gauchi:cea-02399937, TITLE = {{Memory Sizing of a Scalable SRAM In-Memory Computing Tile Based Architecture}}, AUTHOR = {Gauchi, R and Kooli, M and Vivet, P and Noel, J.-P and Beign{\'e}, E. and Mitra, S and Charles, H.-P}, URL = {https://cea.hal.science/cea-02399937}, BOOKTITLE = {{IFIP/IEEE International Conference on Very Large Scale Integration and System-on-Chip (VLSI-SoC)}}, ADDRESS = {Cuzco, Peru}, YEAR = {2019}, MONTH = Oct, KEYWORDS = {In-Memory Computing ; Near Memory Computing ; SRAM ; interconnect ; wire-cost}, PDF = {https://cea.hal.science/cea-02399937/file/VLSI-SoC_2019_paper_no_copyright.pdf}, HAL_ID = {cea-02399937}, HAL_VERSION = {v1}, }