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Adiabatic capacitive logic: A paradigm for low-power logic


Although CMOS technology scaling combined with efficient frequency and voltage scaling strategies offer femto Joule per logic operation, energy consumption remains orders of magnitude above the limit given by information theory. To alleviate this inherent energy dissipation, this paper introduces a new paradigm: the adiabatic capacitive logic. Based on adiabatic operation, the principle also relies on a smooth capacitance modulation to achieve a quasi zero-power logic dissipation. This method limits leakage by using metal-metal junctions instead of semiconductor one. It also avoids dynamic power consumption by adiabatic transitions. The contact-less operation promises a better reliability compared to logic based on nano-mechanical relays.
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hal-01887199 , version 1 (03-10-2018)



Gaël Pillonnet, H. Fanet, S. Houri. Adiabatic capacitive logic: A paradigm for low-power logic. 2017 IEEE International Symposium on Circuits and Systems (ISCAS), May 2017, Baltimore, United States. pp.1-4, ⟨10.1109/ISCAS.2017.8050996⟩. ⟨hal-01887199⟩
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