%0 Journal Article %T A 5500-frames/s 85-GOPS/W 3-D Stacked BSI Vision Chip Based on Parallel In-Focal-Plane Acquisition and Processing %+ Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI) %+ Département d'Architectures, Conception et Logiciels Embarqués-LIST (DACLE-LIST) %+ Département Composants Silicium (DCOS) %A Millet, Laurent %A Chevobbe, Stéphane %A Andriamisaina, Caaliph %A Benaissa, Lamine %A Deschaseaux, Edouard %A Beigné, Edith %A Ben Chehida, Karim %A Lepecq, Maria %A Darouich, Mehdi %A Guellec, Fabrice %A Thomas, Dombek %A Duranton, Marc %Z CEA LETI, Grenoble, France %Z CEA LIST, Saclay, France %< avec comité de lecture %@ 0018-9200 %J IEEE Journal of Solid-State Circuits %I Institute of Electrical and Electronics Engineers %V 54 %N 4 %P 1096-1105 %8 2019 %D 2019 %R 10.1109/JSSC.2018.2886325 %K 3-D stacking %K imager %K parallel computing %K vision chip %Z Engineering Sciences [physics]Journal articles %X This paper presents a 3-D stacked vision chip featuring in-focal-plane read-out tightly coupled with flexible computing architecture for configurable high-speed image analysis. The chip architecture is based on a scalable standalone structure integrating image sensor on the top tier and processing elements (PEs) plus memories in the bottom tier. By using 3-D stacking partitioning, our prototype benefits from backside illuminated pixels sensitivity, a fully parallel communication between image sensor and PEs for low-latency performances, while leaving enough room in the bottom tier to embed advanced computing features. One scalable structure embeds a 16x16 pixel array (or 64 x 64 pixels in high-resolution mode), associated with an 8-bit single instruction multiple data (SIMD) processor; fabricated in dual 130-nm 1P6M CMOS process. This paper exhibits a 5500 frames/s and 85 giga operations per second (GOPS)/W in low-resolution mode, with large kernels capabilities through eight directions interpixel communication. Multiflow capability is also demonstrated to execute different programs in different areas of the vision chip. %G English %L cea-02186449 %U https://cea.hal.science/cea-02186449 %~ CEA %~ DSV %~ DRT %~ UNIV-PARIS-SACLAY %~ CEA-DRF %~ LETI %~ LIST %~ CEA-GRE %~ GS-ENGINEERING %~ GS-COMPUTER-SCIENCE %~ DSCIN