%0 Conference Proceedings %T A new parallel SystemC kernel leveraging manycore architectures %+ Département d'Architectures, Conception et Logiciels Embarqués-LIST (DACLE-LIST) %A Ventroux, N. %A Sassolas, T. %Z Conference of 19th Design, Automation and Test in Europe Conference and Exhibition, DATE 2016 ; Conference Date: 14 March 2016 Through 18 March 2016; Conference Code:121520 %< avec comité de lecture %B 19th Design, Automation and Test in Europe Conference and Exhibition, DATE 2016 %C Dresden, Germany %I Institute of Electrical and Electronics Engineers Inc. %P 487-492 %8 2016-03-14 %D 2016 %K System theory %K System-on-chip %K Development costs %K Electronic system level design %K Many-core architecture %K Maximum acceleration %K Parallel evaluation %K Simulation performance %K Single-thread performance %K System-level modeling %K Parallel architectures %Z Computer Science [cs]Conference papers %X The complexity of system-level modeling is continuously increasing. Electronic System Level (ESL) design requires fast simulation techniques to control future SoC development cost and time-to-market. However, SystemC simulations are sequential and then limited by single-thread performance. In this paper, we present a new parallel SystemC kernel that efficiently leverages the multiple cores of a host machine, reaching high simulation performance without relaxing accuracy. It supports atomic parallel evaluation of SystemC processes and repeatable execution for HW/SW debugging. This new kernel is fully compliant with existing standards and easy to integrate in any existing SystemC model. Evaluations show a maximum acceleration of 34× compared to Accellera SystemC on a 64-core AMD Opteron machine. %G English %L cea-01843186 %U https://cea.hal.science/cea-01843186 %~ CEA %~ DRT %~ UNIV-PARIS-SACLAY %~ LIST %~ GS-ENGINEERING %~ GS-COMPUTER-SCIENCE %~ DSCIN