%0 Conference Proceedings %T Reducing the Contention Experienced by Real-Time Core-to-I/O Flows over a Tilera-Like Network on Chip %+ Département d'Architectures, Conception et Logiciels Embarqués-LIST (DACLE-LIST) %+ Réseaux, Mobiles, Embarqués, Sans fil, Satellites (IRIT-RMESS) %+ Institut National Polytechnique (Toulouse) (Toulouse INP) %A Abdallah, L. %A Jan, M. %A Ermont, Jérôme %A Fraboul, Christian %Z Conference of 28th Euromicro Conference on Real-Time Systems, ECRTS 2016 ; Conference Date: 5 July 2016 Through 8 July 2016; Conference Code:123641 %< avec comité de lecture %B 2016 28th Euromicro Conference on Real-Time Systems (ECRTS) %C Toulouse, Unknown Region %I Institute of Electrical and Electronics Engineers Inc. %V 2016-August %P 86-96 %8 2016-07-05 %D 2016 %R 10.1109/ECRTS.2016.9 %K Computer architecture %K Embedded systems %K Ethernet %K Interactive computer systems %K Mapping %K Network-on-chip %K Servers %K Telecommunication networks %K Avionics applications %K Contention-aware %K Critical applications %K Embedded real time systems %K Input/output interface %K Many-core architecture %K Traversal time %K Wormhole switching %K Real time systems %Z Computer Science [cs] %Z Engineering Sciences [physics]Conference papers %X Many-core architectures are promising hardware to design real-time systems. However, the worst-case behavior of the Network-on-Chip (NoC) for both core-to-core and core-to-Input/Output (I/O) communications of critical applications must be established. The mapping over the NoC of both critical and non-critical applications has an impact on the network contention these critical communications exhibit. So far, all existing mapping strategies have focused on core-to-core communications. However, many-cores in embedded real-time systems will be integrated within backbone Ethernet networks, as they mostly provide Ethernet controllers as I/O interfaces. In a previous work we have shown that Ethernet packets can be dropped due to an internal congestion in a Tilera-like NoC. In this work, we describe and evaluate a mapping strategy for such Tilera-like NoCs that minimizes the contention of core-to-I/O critical flows in order to solve this problem. Experimental results on real avionics applications show significant improvements of core-to-IO flows transmission delays, without significantly impacting transmission delays of core-to-core flows. %G English %L cea-01838135 %U https://cea.hal.science/cea-01838135 %~ CEA %~ UNIV-TLSE2 %~ UNIV-TLSE3 %~ CNRS %~ SMS %~ UT1-CAPITOLE %~ DRT %~ UNIV-PARIS-SACLAY %~ LIST %~ IRIT %~ IRIT-RMESS %~ GS-ENGINEERING %~ IRIT-ASR %~ GS-COMPUTER-SCIENCE %~ DSCIN %~ TOULOUSE-INP %~ UNIV-UT3 %~ UT3-INP %~ UT3-TOULOUSEINP