Many-core processors are made by hundreds to thousands cores, distributed memories and a dedicated network on a single chip. In this context, and because of the scale of the processor, providing a shared memory system has to rely on efficient hardware mechanisms and/or data consistency protocols. Some works explored several consistency mechanisms designed for many-core processors. They lead to the conclusion that there won't exist one protocol that fits to all applications and hardware contexts. Therefore, it sounds relevant to use a multi-protocol platform, in which shared data of the application can be managed by different protocols. Protocols are chosen and configured at compile time, following a static analysis of the application and the profiling of memory accesses. In this work, we propose a high-level timed model that we use to evaluate, at compile time, the consistency protocol which has been assigned to a given application and a given Network-on-Chip (NoC). This model allows to calculate the number of NoC cycles needed for each data access, that can be turned into mean access cycles for each core or each shared data. The model is not as accurate as a cycle-based NoC simulator or an instruction set simulator. However, it is accurate enough to evaluate the impact of choosing and configuring a protocol, and its lightweight implementation allows to run within an operational research optimization loop. To validate our approach, we apply the model to compare three consistency protocols, on a 2D mesh network, compiling a parallel convolution application. Copyright is held by the owner/author(s).